This video, part 4 of the BMS Design Series, focuses on creating a functional schematic for a 5-series lithium-ion Battery Management System using the BQ77915 chipset. The speaker emphasizes designing a BMS based on its architecture and functionality, rather than general schematic drawing tutorials. Key components are selected, including the BQ77915 non-smart chipset (chosen for cost-effectiveness), a 1.5 milliohm current sense resistor for 20A continuous and 46A pulse current, and AON6144 FETs for their low on-resistance and voltage tolerance. Detailed calculations and considerations derived from the datasheet are crucial for each component. The design incorporates features like internal cell balancing, overcurrent protection (23A continuous, 46A pulse), and short-circuit protection (120A spike within 960µs). The speaker demonstrates the practical steps of laying out the schematic in Altium Designer, including connecting cell inputs, configuring power lines, and setting up FET drive circuitry, ensuring proper connections and stable operation. The video highlights the importance of precise component selection (e.g., 1% resistors) and adherence to industry best practices like Kelvin connections for current sensing and avoiding quad junctions in schematics.
Type: A non-smart, or "dumb," chipset is chosen, meaning it has pre-programmed settings and cannot be programmed via software like smart chips (e.g., BQ40Z50, 40Z80).
Configuration: Settings for overvoltage, undervoltage, overcurrent, short-circuit, and temperature are selected from a fixed table (e.g., 1501 SKU chosen for 4.25V overvoltage and 2.8V undervoltage thresholds).
BQ77915 Device Comparison Table with Pre-Programmed Values
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Cost-effectiveness: Non-smart chips are significantly cheaper ($1 vs $2-3 for smart chips in large quantities), making them ideal for high-volume production if specific parameters are acceptable.
Principle: The BMS measures voltage drop across a current sense resistor to determine current. The chip's thresholds (e.g., 35mV for overcurrent discharge 1, 60mV for overcurrent discharge 2) are hardware-set.
Calculation:
For a 20A continuous current and a 35mV threshold, a 1.75 milliohm resistor is needed (35mV / 20A).
A more common 1.5 milliohm resistor is selected, resulting in a 23.33A trip point for overcurrent discharge 1 and 46.66A for overcurrent discharge 2 (which is double the first threshold).
Decision: A 1.5 milliohm current sense resistor is noted for the schematic.
Low on-resistance: Minimizes voltage drop and heat dissipation for continuous current (20A).
Voltage tolerance: Must be sufficient for the pack voltage (e.g., 40V FET for a 21V pack).
Gate-to-Source Voltage: Ensure the BMS chip can properly drive the FETs into full conduction.
Short-circuit Current Handling: FETs must tolerate high current spikes (e.g., 120A for the P26A cell) and cut off within specified times (e.g., 960µs). The AON6144 is suitable for this, preventing "burning up" during hard current stops.
Quantity: Two pairs of FETs are used to enhance continuous and short-circuit current handling.
Fuse Selection: A standard 30A off-the-shelf fuse is chosen.
Recommended Operating Conditions [12:35]: Lists typical operating currents (80-115 µA in normal mode, 3 µA in hibernate, 500 nA in shutdown).
Device Configuration Table [14:00]: Explains that different SKUs of the chip (e.g., -01, -02, -04) have different pre-programmed voltage, current, and temperature thresholds, which cannot be changed by the user. Texas Instruments offers custom SKUs for high-volume orders.
Overcurrent Discharge Programming [22:06]: While internal thresholds are fixed, the delay options for overcurrent discharge 1 (OCD1) and 2 (OCD2) can be programmed externally using a resistor on the OCDP pin.
A 750kΩ resistor is selected for the OCDP pin to achieve the longest possible delays: 1420ms for OCD1 (23A threshold) and 700ms for OCD2 (46A threshold), ensuring the higher current pulse has a shorter trip time.
Overcurrent Discharge Programming Table with Timing Values
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The video delves into specific functional aspects and operational modes of the BQ77915.
Protection Summary [20:20]: Two internal comparators manage voltage (OV, UV) and current (OCD, SCD, OC) protections.
State Comparator Summary in Fault Conditions
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Recovery Options [20:50]: Explains how the BMS recovers from fault conditions (e.g., load removal or time expiration) and emphasizes the importance of avoiding constant short-circuit attempts that can degrade MOSFETs.
Temperature Protection [29:55]: Discussion on how the chip operates under various temperature conditions (overtemperature/undertemperature in charge/discharge).
BQ77915 Operation in OTC/OTD/UTC/UTD Tables
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Internal vs. External: The chip supports both internal and external cell balancing. Internal balancing is used in this design.
Activation: Cell balancing is enabled by connecting the CB1 pin to VSS. Leaving it floating disables balancing.
Current Control: The R_INI series resistors on the cell inputs control the balancing current. A value of 100 ohms is chosen to provide approximately 35mA of balancing current (based on a 3.8V cell balance turn-on threshold).
Concept: Multiple BQ77915 chips can be stacked to manage higher cell count battery packs (from 3 to 20+ series). The ground reference of an upper chip connects to the positive terminal of the cell monitored by the chip below it.
Design Consideration: Series diodes are crucial between stacked chips to prevent reverse current flow and voltage potential issues, especially when switching.
BQ77915 10-Series Configuration with Internal Cell Balancing
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Power-On Reset: The chip performs self-checks during boot-up.
Normal Mode: Charge and discharge are enabled, and cell balancing can occur.
Fault Mode: Triggered by comparator circuits; turns off charge/discharge FETs until recovery.
Hibernate Mode: Low-power mode, activated by driving the System Present (PRES) pin high. This allows the battery pack to be "turned off" to prevent draining when idle.
Shutdown Mode: Occurs when cell voltage drops below a critical threshold, completely disabling output for safety.
BQ77915 Device Operational States Flowchart
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Customer Fast Protection Test Modes [59:31]: A unique feature that allows rapid testing of fault conditions by overriding recovery times. This speeds up manufacturing test processes by quickly cycling through protection triggers.
Charge/Discharge FET Protection [1:07:09]: Explains the need for proper gate drive resistors and pull-down resistors to ensure FETs turn off quickly under high current conditions, preventing degradation. A Zener diode can be used across the FET gate-source to protect against overvoltage.
Recommended System Implementation of FETs
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Load Detection (LD) [1:11:33]: The LD pin detects if a load is connected to the battery output. This prevents auto-recovery from certain faults (e.g., undervoltage, overcurrent in discharge) until the load is removed, ensuring safety and preventing rapid cycling.
The video transitions to the practical implementation of the schematic in Altium Designer.
Software: Altium Designer is used, leveraging its manufacturer part search feature for component data.
Real-world Example [1:26:37]: The speaker demonstrates a physical battery pack with a custom BMS designed by their team.
Speaker showing a real-world battery pack with BMS
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General Layout Principles: Emphasizes neatness, clear organization (power flowing one way, signals another), and avoidance of "quad junctions" (where four wires meet at one point) for clarity and to prevent software interpretation errors.
Main Components Placement:
BQ77915 chipset is placed centrally.
Input connector for cell sense lines.
Four AON6144 FETs (two for charge, two for discharge) are placed.
Output pads and fuse.
Connectors for system present switch and thermistors for an external charger.
BQ77915EVM Schematic as Design Reference
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A common filter circuit is implemented with two 0.1µF capacitors to ground and one 0.1µF capacitor across the SRP/SRN lines.
Kelvin Connections: Stress is placed on making very short, direct connections from the SRP/SRN pins to the pads of the current sense resistor to maintain accuracy.
Initial FET Placement: FETs connected to the current sense resistor.
Charge/Discharge FETs and Current Sense Connection
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Discharge FETs: Driven by the DSG pin through a 5.1kΩ series resistor and a 1MΩ pull-down resistor. Additional 51Ω resistors are added for each FET when paralleling to prevent ringing.
Discharge FETs with Individual Gate Resistors
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Discharge FET Path to Current Sense Resistor
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Charge FETs: Driven by the CHG pin through a 5.1kΩ series resistor, a 3MΩ pull-down resistor, and protected by a 16V Zener diode (value chosen from evaluation module).
OCDP: Connected to batt- via a 750kΩ resistor for the calculated overcurrent discharge delay.
PRES: Connected to pack+ via a 10kΩ pull-up resistor for an external power switch.
OCDP and Thermistor Sensor (TS) Pin Connections
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TS: Connected to VTB (highest cell voltage reference) via a 10kΩ resistor, with its output tied to an external thermistor connector for charger communication.
External Thermistor Connections on the Schematic
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Simplified Schematic with Design Parameters
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CCFG: Left floating to configure the chip for 5-series operation.
LPWR & CBO: Left floating as they are for stacking implementations which are not used in this single-chip design.
CBO and LPWR Pins Handled by "No ERC" Directives
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CTR_C & CTR_D: Connected directly to ground as stacking is not being used.
Additional 0.1µF capacitors are placed between the output terminals for stability and between FET drains and sources to prevent ringing.
The schematic is then automatically annotated, assigning unique designators (e.g., R1, C1, D1) to all components.
The completed schematic provides a 5-series BMS capable of handling up to 23A continuous current with 46A spikes, two thermistors, and a power on/off switch.
